1. Technical Field
The present invention relates in general to a system and method for message delivery across a plurality of processors. More particularly, the present invention relates to a system and method for using ring queues to manage interrupt requests that are received from the plurality of processors.
2. Description of the Related Art
Computer systems are becoming more and more complex. The computer industry typically doubles the performance of a computer system every 18 months (e.g. personal computer, PDA, gaming console). In order for the computer industry to accomplish this task, the semiconductor industry produces integrated circuits that double in performance every 18 months. A computer system uses integrated circuits for particular functions based upon the integrated circuits' architecture. Two fundamental architectures are 1) microprocessor-based and 2) digital signal processor-based.
An integrated circuit with a microprocessor-based architecture is typically used to handle control operations whereas an integrated circuit with a digital signal processor-based architecture is typically designed to handle signal-processing manipulations (i.e. mathematical operations). As technology evolves, the computer industry and the semiconductor industry realize the importance of using both architectures, or processor types, in a computer system design.
The computer industry is moving towards a multi-processor architecture which includes a main processor to execute a main operating system, and one or more support processors to support application tasks. The main processor typically executes a main operating system, and invokes application programs. In turn, the application programs use the support processors for offloading particular tasks. A challenge found in multi-processor architectures, however, is managing interrupts that are received from the support processors. The amount of interrupts that occur in a computer system increases linearly as the number of processors increase. For example, if a computer system includes one main processor and eight support processors, the amount of interrupts that the processors generate may be eight times more than a computer system that includes only one processor.
Another challenge found with multi-processor interrupt management is the ability to track interrupt sequence. For example, an application may use four support processors for task execution, and each of the support processors send interrupts to the main processor. In this example, if the main processor does not manage the order in which the interrupts were received, the application may process the interrupts out of order and, in turn, generate erroneous results.
In addition, a challenge found with existing art is that if a main processor receives multiple identical event interrupts, the main processor typically combines the multiple identical event interrupts into one interrupt. This causes problems if, for example, four support processors each send an identical interrupt, and each of the identical interrupts is combined into a single interrupt.
Furthermore, a challenge found with existing art is that interrupts that are received from support processors include little or no data. This approach may force an application to spend time retrieving data from memory in order to process the corresponding interrupt.
What is needed, therefore, is a system and method to effectively manage interrupt requests in a multi-processor environment while minimizing interrupt processing load.